SIAM Journal on Discrete Mathematics


Minimizing Wirelength in Zero and Bounded Skew Clock Trees

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History

Published online: 01 August 2006

Publication Data

ISSN (print): 0895-4801
ISSN (online): 1095-7146
CODEN: sjdmec

An important problem in VLSI design is distributing a clock signal to synchronous elements in a VLSI circuit so that the signal arrives at all elements simultaneously. The signal is distributed by means of a clock routing tree rooted at a global clock source. The difference in length between the longest and shortest root-leaf path is called the skew of the tree. The problem is to construct a clock tree with zero skew (to achieve synchronicity) and minimal sum of edge lengths (so that circuit area and clock tree capacitance are minimized).

We give the first constant-factor approximation algorithms for this problem and its variants that arise in the VLSI context. For the zero skew problem in general metric spaces, we give an approximation algorithm with a performance guarantee of 2e. For the L1 version on the plane, we give an (8/ln 2)-approximation algorithm.

Copyright © 2004 Society for Industrial and Applied Mathematics

Cited by

The associative-skew clock routing problem. 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051), 168-172. CrossRef