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2015 Proceedings of the Twelfth Workshop on Analytic Algorithmics and Combinatorics (ANALCO)

Analysis of Branch Misses in Quicksort

Abstract

The analysis of algorithms mostly relies on counting classic elementary operations like additions, multiplications, comparisons, swaps etc. This approach is often sufficient to quantify an algorithm's efficiency. In some cases, however, features of modern processor architectures like pipelined execution and memory hierarchies have significant impact on running time and need to be taken into account to get a reliable picture. One such example is Quicksort: It has been demonstrated experimentally that under certain conditions on the hardware the classically optimal balanced choice of the pivot as median of a sample gets harmful. The reason lies in mispredicted branches whose rollback costs become dominating.
In this paper, we give the first precise analytical investigation of the influence of pipelining and the resulting branch mispredictions on the efficiency of (classic) Quicksort and Yaroslavskiy's dual-pivot Quicksort as implemented in Oracle's Java 7 library. For the latter it is still not fully understood why experiments prove it 10% faster than a highly engineered implementation of a classic single-pivot version. For different branch prediction strategies, we give precise asymptotics for the expected number of branch misses caused by the aforementioned Quicksort variants when their pivots are chosen from a sample of the input. We conclude that the difference in branch misses is too small to explain the superiority of the dual-pivot algorithm.

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cover image Proceedings
2015 Proceedings of the Twelfth Workshop on Analytic Algorithmics and Combinatorics (ANALCO)
Pages: 114 - 128
Editors: Robert Sedgewick, Princeton University, Princeton, New Jersey, USA and Mark Daniel Ward, Purdue University, West Lafayette, Indiana, USA
ISBN (Online): 978-1-61197-376-1

History

Submitted: 11 November 2014
Published online: 22 December 2014

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*
Part of this research was done during a visit at UPC, for which the second and third authors acknowledge support by project TIN2007-66523 Formal methods and algorithms for system design (FORMALISM) of the Spanish Ministry of Economy and Competitiveness

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